So far silicon is the most popular material in the semiconductor industry. It is also the most mature material in the fabrication of semiconductor devices and microcircuits. Since its luminescent efficiency is extremely low due to its property of indirect energy gap, it is impossible for it to be applied directly to the fabrication process of optoelectronic devices. After it was discovered that porous silicon has the property of direct energy gap because of its zone folding and quantum confinement effects, and has an intense visible photoluminescene spectrum, application of the porous silicon material in optoelectronic devices was widely studied. It is necessary to reduce the porous silicon optoelectronic devices in concert with the present VLSI skill for developing the optoelectronic integrated circuits of silicon.
Generally speaking, the benefits for the fabrication process of porous silicon are easy to fabricate, low cost and able to avoid the problems of lattice mismatch, expensive price and much timeconsuming in fabricating the optoelectronic integrated circuit with previous compound semiconductors. It is worthwhile in the market if the porous silicon optoelectronic devices are applied to the mature silicon integrated circuit, and their fabrication process could be significantly simplified. But there are some shortcomings in finishing the necessary miniaturing process of porous silicon optoelectronic devices. For it is necessary to face a fundamental problem that a prior masking layer has either a lifetime too short or a utility quality too poor in the conventional fabrication process of the porous silicon for size-reducing porous silicon optoelectronic devices. In other words: the disadvantages still exist in the prior art though they can size-reduce the porous silicon optoelectronic devices.
Now we talk about general masking layers applied to finish the size-reducing purpose for defining the growing region of porous silicon. The size-reducing skill can be classified into two types: one is the traditional photolithography and the other is the non-traditional skill. The former includes masking layers respectively formed by silicon oxide, silicon nitride and silicon carbide. But the disadvantages of these masking layers are: the SiO.sub.2 masking layer would dissolve immediately in the HF acidic solution, and cannot be used because of its too short lifetime; and the porous silicon formed by anodic-oxidation etching on the silicon substrate under the Si.sub.3 N.sub.4 masking layer, which cannot dissolve in the HF acidic solution, is easy to strip off because of the undercut phenomenon resulting in a distorted defined region under Si.sub.3 N.sub.4 /Si interface having no depletion region as a result of isotropic etching.
As shown in Prior Art FIGS. 1(a)-1(d), they are the photographs by scanning electron microscope, in which the silicon nitride masking layer is used to define the patterned porous silicon. The silicon nitride masking layer is grown by low pressure chemical vapor deposition, and its pattern is formed by wet chemical etching. Prior Art FIGS. 1(a)-1(d) are scanning electron microscope photographs magnified by the scale of 2,000 times, in which the bar scales are all 10 .mu.m and 2 mm represents 1 .mu.m. Prior Art FIGS. 1(a)-1(d) show the formations of the defined patterned region of porous silicon 101 under the silicon nitride masking layers 204, as shown in the figures in which the dark bands are porous silicon 101 and the bright bands are masking layers 204. The area A in FIG. 1(b) is the porous silicon 101, the area B is the silicon nitride masking layer 204 and the area C is the silicon substrate 10.
The anodization times in these figures are respectively: one minute for Prior Art FIG. 1(a), two minutes for Prior Art FIG. 1(b), three minutes for Prior Art FIG. 1(c) and five minutes for Prior Art FIG. 1(d). The accompanied growing conditions of the porous silicon are: current density 3.5 mA/cm.sup.2, and the anodization solution of a mixture of 30 vol. % HF and 70 vol. % H.sub.2 O, in which the HF concentration is 49 wt. %. In Prior Art FIGS. 1(a)-1(d), it is apparent that the longer the anodization time, the more serious the distortion of the patterned porous silicon.
Referring now to Prior Art FIGS. 2(a) and (b), they are the scanning electron microscope photographs for a cross-section of patterned porous silicon under the silicon nitride mask in Prior Art FIG. 1(d). Prior Art FIG. 2(b) is a locally amplified photogragh of Prior Art FIG. 2(a). Prior Art FIG. 2(a) is magnified by 6000 times, in which the bar scale is 1 .mu.m and 0.6 cm represents 1 .mu.m. Prior Art FIG. 2(b) is magnified by 20,000 times, which is an amplified photograph of Prior Art FIG. 2(a) and its bar scale is 1 .mu.m. We should note that Prior Art FIG. 2(a) is the cross-sectional scanning electron microscope scanning photograph of Prior Art FIG. 1(d), which shows that the patterned porous silicon 101 on the silicon substrate 10 is defined by utilizing the silicon nitride mask and the electrolytic conditions are the same as those in Prior Art FIG. 1(d).
It is apparent that the transverse growth size and the vertical growth size of the porous silicon under the silicon nitride masking layer are almost in the ratio of 1.3:1 after the electrolytic process in Prior Art FIG. 2(b). The part of the silicon nitride film on the transverse growth region of the porous silicon is slightly stripped off in Prior Art FIG. 1(d), which is really a worse condition since the porous silicon growth will be more isotropic. For this reason, we know the silicon nitride masking layer is not proper to be used to define the patterned porous silicon. In a similar condition, the short lifetime and serious distortion also exist in the masks of silicon oxide and silicon carbide, so all the masking layers are not practical. The isotropic growth, short lifetime and serious distortion are main defects of the conventional photolithography.
Now we consider the non-traditional skill, such as the ion irradiation, photoanodic etching, focused ion beam implantation and amorphization. This type would lead to destruction in non-porous silicon growth region, so it is worse than the conventional type discussed above for the fabrication of optoelectronic integrated circuit. And it is not practical and improper to modern integrated circuit, in avoiding the complex followed fabrication process, such as recrystallization or planarization to recover the original crystal structure having no grown porous silicon region.
It is therefore tried by the applicant to deal with the above shortcomings suffered by the prior mask skills.